ASIC Design for Signal Processing

Contents

Introduction
Digital Circuit Design
Carry-Save Arithmetic
Booth Recoding
Patent Pending
Multipliers
Complex Multipliers
Matrix Multipliers
Hermitian Matrices
Signal Processor
Links and Contact

    Motivation
    An ASIC Design
    For Signal Processing
    Aims of the project
    Scope of the project
    Results

    Design Process
    FPGAs
    ASICs

3:2 Compressors
4:2 Compressors

    Shift & Add
    Recoding
    Sign Extension Tricks

    Beating the Optimal
    Coding Style
    Alternatives

Main Design
Alteratives

    Architectures
    Memory Configuration
    Implementation
    Double Buffering
    Non-Comformities
    Squaring

    Taking Advantage
    multiplication
    any combination

Clamping
Disabling rows

    Contact
    Acknowledgements
    Download
    Errata
    Sites of Interest
    Reference Links

Patent : Multiplier Enhancement

[Last modified 11:12:57 PM on Tuesday, 27 July 2010]
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